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HIP9010
Data Sheet November 1998 File Number 3601.4
Engine Knock Signal Processor
The HIP9010 is used to provide a method of detecting premature detonation or "Knock" in automotive engines. A block diagram of this IC is shown in Figure 1. The chip alternately selects one of the two sensors mounted on the engine block. Two programmable bandpass filters process the signal from both sensors, and divides the signal into two channels. When the engine is not knocking, programmable gain adjust stages are set to ensure that both the reference channel and the knock channel contain similar energies. This technique ensures that the detection system is comparatively immune to changes in the engine background noise level. When the engine is knocking, the energy in the knock channel increases.
Features
* Two Sensor Inputs * Microprocessor Programmable * Accurate and Stable Filter Elements * Digitally Programmable Gain * Digitally Programmable Time Constants * Digitally Programmable Filter Characteristics * On-Chip Clock * Operating Temperature Range -40oC to 125oC
Applications
* Engine Knock Detector Processor * Analog Signal Processing where Controllable Filter Characteristics are Required
Ordering Information
PART NUMBER HIP9010AB TEMP. RANGE (oC) -40 to 125 PACKAGE 20 Ld SOIC (W) PKG. NO. M20.3
Pinout
HIP9010 (SOIC) TOP VIEW
VDD GND VMID INOUT NC NC INT/HOLD CS OSCIN
1 2 3 4 5 6 7 8 9
20 S0IN 19 S0FB 18 S1FB 17 S1IN 16 NC 15 NC 14 TEST 13 SCK 12 MOSI 11 MISO
OSCOUT 10
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
Simplified Block Diagram
REFERENCE FREQUENCY CHANNEL DIFFERENTIAL TO SINGLE-ENDED CONVERTER AND OUTPUT DRIVER INOUT (4)
4-2
(19) S0FB (20) S0IN
PROGRAMMABLE BANDPASS FILTER 1-20kHz 64 STEPS
PROGRAMMABLE GAIN STAGE 1-0.133 64 STEPS
ACTIVE FULL WAVE RECTIFIER
CHANNEL SELECT SWITCHES +
3RD ORDER ANTIALIASING FILTER
(18) S1FB
PROGRAMMABLE INTEGRATOR 40-600s 32 STEPS
HIP9010
(17) S1IN
+
POWER SUPPLY AND BIAS CIRCUITS
PROGRAMMABLE BANDPASS FILTER 1-20kHz 64 STEPS
PROGRAMMABLE STAGE GAIN 1-0.133 64 STEPS
OSCIN (9) ACTIVE FULL WAVE RECTIFIER CLOCK TO SWITCHED CAPACITOR NETWORKS OSCOUT (10)
SCK (13) CS (8)
KNOCK FREQUENCY CHANNEL
REGISTERS AND STATE MACHINE (14) TEST
SPI INTERSPACE
MOSI (12) MISO (11) INT/HOLD (7)
(3) VMID
(1) VDD (2) GND
FIGURE 1.
HIP9010
Absolute Maximum Ratings
DC Logic Supply, VDD . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V (Max)
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Storage Temperature Range, TSTG . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Lead Temperature (Soldering) . . . . . . . . . . . . . . . 300oC At distance 1/16in 1/32in (1.59mm 0.79mm) from case for 10s (Max) (SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
VDD = 5V, 5%, GND = 0V, Clock Frequency 4MHz, 0.5%, TA = -40oC to 125oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
DC ELECTRICAL CHARACTERISTICS Quiescent Supply Current Midpoint Voltage, Pin 3 Midpoint Voltage, Pin 3 Input Leakage, Pin 14 Internal Pull-Up Resistance, Pin 14 Leakage of Pins 7, 8, 12 and 13 Low Input Voltage, Pins 7, 8, 12 and 13 High Input Voltage, Pins 7, 8, 12 and 13 Low Level Output, Pin 11 Leakage Pin 11 Low Level Output, Pin 10 High Level Output, Pin 10 INPUT AMPLIFIERS S0FB and S1FB High Output Voltage S0FB and S1FB Low Output Voltage S0FB and S1FB Closed Loop S0FB and S1FB Closed Loop ANTIALIASING FILTER Response 1kHz to 20kHz, Referenced to 1kHz Attenuation at 180kHz Referenced to 1kHz PROGRAMMABLE FILTERS Peak to Peak Voltage Output Filters Q (Note 2) PROGRAMMABLE GAIN AMPLIFIERS Percent Amplifier Gain Deviation Per Table 2 %G Run Mode 1 % VOUTP-P Q Run Mode Run Mode 3.5 4.0 2.5 VP-P Q BW ATEN Test Mode, 70mVRMS Input to S0FB or S1FB, Output Pin 4 Test Mode, 70mVRMS Input to S0FB or S1FB, Output Pin 4 -10 -2 -15 dB dB VOUTHI VOUTLO ACL ACL 100A ISINK, VDD = 5V 100A ISOURCE, VDD = 5V Input Resistor = 1M, Feedback Resistor = 49.9k Input Resistor = 47.5k, Feedback Resistor = 475k 4.7 -25 18 4.9 15 -26 20 200 -27 21 V mV dB dB IDD VMID VMID ILTEST RTEST IL VIL VIH VOL IL VOL VOH ISOURCE = 4mA Measured at GND and VDD = 5V ISOURCE = 500A, VDD = 5V ISINK = -500A, VDD = 5V VDD = 5.25V, GND = 0V VDD = 5.0V, IL = 2mA Source VDD = 5.0V, IL = 0mA Measured at VDD = 5.0V VDD = 5.0V, I Measure = 15A Measured at GND and VDD = 5V 3 2.3 2.4 30 70 0.01 4.4 7.5 2.45 2.5 100 12 2.55 2.6 3 200 3 30 0.30 10 1.5 mA V V A K A % of VDD % of VDD V A V V
4-3
HIP9010
Electrical Specifications
PARAMETER INTEGRATOR Integrator Offset Voltage Integrator Reset Voltage Integrator Droop after 500s OUTPUT AND SAMPLE AND HOLD Differential to Single Ended Converter Offset Voltage Change in Converter Output SYSTEM GAIN DEVIATION Gain Deviation from "Ideal Equation" Correlation, Factor - 5.0% VOUT VRESET Run Mode, maximum signal output from Input Amplifier <2.25VP-P, Equation Output x 0.95 + Device Reset Voltage. For Total VOUT 4.7V -8%, 100mV Equation x 0.95 -VRESET 8%, 100mV V DIFVIO DIFOUT By Design Run Mode, 500A, Sinking to No Load 0.1 1 3 mV mV INTGVIO VRESET VDROOP By Design Pin 4 Voltage at Initiation of Integration Cycle. VDD = 5V Hold Mode, Pin 7 = 0V, VDD = 5V, Pin 4 set to 20% to 80% of VDD 430 0.1 500 3 570 50 mV mV mV VDD = 5V, 5%, GND = 0V, Clock Frequency 4MHz, 0.5%, TA = -40oC to 125oC, Unless Otherwise Specified (Continued) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
NOTE: 2. Q = fO /BW, Where: fO = Center Frequency, BW = 3dB bandwidth.
Ideal Equation
RF N N INTOUT ( volts ) = Input signal (V P - P ) x --------- G K x 1.273 x -------------------------------------------------- - G R x 1.273 x -------------------------------------------------- + V RESET R IN TC (ms) x f Q (kHz) TC (ms) x f Q (kHz) When the two filters are set to the same frequency and the input signal is present for the periods TIN, then: RF T IN INTOUT ( volts ) = Input signal (V P - P ) x --------- 1.273 x -------- ( G K - G R ) + V RESET R IN TC GR and GK = Programed Gain of Reference and Knock channels. TIN = Time input signal is present In ms. TC = Programmed integrator time constant ms. N = Number of cycles of input signal. fQ = Frequency of input signal. Assumes both filters are programmed to the same frequency. VRESET = Integrator Reset Voltage. 1.273 = 4/ RF = Feedback resistor value. RIN = Signal input resistor value. For example, assume 300mVP-P input with the time constant programmed to 300s and the Integration time is 1.2ms. The RF/RIN ratio is one and the Reference channel is programmed to a Gain of 0.188. The Knock channel is then automatically set to a gain of one. The input signal is continuous for the total integration time, TIN. 1.2ms INTOUT ( volts ) = 0.3V (V P - P ) x 1.273 x ----------------------- x ( 1.000 - 0.188 ) + V RESET = 1.24V + 0.500V = 1.74V 0.300ms
4-4
HIP9010
+5V C3, 0.022F GND MOSI C2, 3.3nF S1IN R2 C1, 3.3nF R1 TRANSDUCERS 20pF 4MHz OSCOUT 20pF 1M A/D CONVERTER INTOUT R3 OSCIN R4 S0IN S0FB TEST S1FB MISO SCK CS INT/HOLD SPI BUS VDD VMID
HIP9010
MICROPROCESSOR
FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE HIP9010 IN AN AUTOMOTIVE APPLICATION
Pin Descriptions
PIN NUMBER 1 2 3 4 5 and 6 7 8 9 10 11 12 13 14 15 and 16 17 18 19 20 SYMBOL VDD GND VMID INTOUT NC INT/HOLD CS OSCIN OSCOUT MISO MOSI SCK TEST NC S1IN S1FB S0FB S0IN 5V power input. This terminal is tied to ground. This terminal is tied to the internal mid-supply generator and is brought out for supply bypassing by a 0.022F capacitor. Buffered output of the integrator. These terminals are not internally connected. DO NOT USE. Selects whether the chip is in the Integrate Mode (Input High) or in the Hold Mode (Input Low). A low input on this pin enables the chip to communicate over the SPI bus. Input to inverter used for the oscillator circuit. A 4MHz crystal or ceramic resonator is connected between this pin and pin 10. To bias the inverter, a 1.0M to 10M resistor is usually connected between this pin and pin 10. Output of the inverter used for the oscillator. See pin 9 above. Output of the chip SPI data bus. It is the inversion of the chip DATAIN line. This is an open drain output. The output must be disabled by placing the CS High when the chip is not selected. Input of the chip SPI data bus. Data length is eight bits. Input from the SPI clock. Normally high, the data is clocked to the chip internal circuitry on the rising clock edge. A low on this pin places the chip in the test mode. For normal operation this terminal is tied high or left open. These terminals are not internally connected. DO NOT USE. Inverting input to sensor one amplifier. A resistor is tied from this summing input to the transducer. A second resistor is tied between this terminal and terminal 18, S1FB to establish the gain of the amplifier. Output of the sensor one amplifier. This terminal is used to apply feedback. Output of the sensor zero amplifier. This terminal is used to apply feedback. Inverting input to sensor zero amplifier. A resistor is tied from this summing input to the transducer. A second resistor is tied between this terminal and terminal 19, S0FB to establish the gain of the amplifier. DESCRIPTION
4-5
HIP9010 Description of the HIP9010 Operation
This IC is designed to be a universal digitally controlled, analog interface between engine acoustical sensors or accelerometers and internal combustion engine fuel management systems. Two wideband input amplifiers are provided that allow the use of two sensors that may be of the piezoelectric type that can be mounted in optimum locations on either in-line or V-type engine configurations. Output from these amplifiers is directed from a channel select switch into both digitally controlled filter and amplifier channels. Both filter bandpass and gain settings are programmable from a microprocessor. Output from the two channels is combined in a digitally programmable integrator. Integrator output is applied to a line driver for further processing by the engine fuel management system. Broadband piezoelectric ceramic transducers used for the engine signal pickup have device capacitances in the order of 1100pF and output voltages that range from 5mV to 8VRMS. During normal engine operation a single input channel is selected and applied to the filters. One filter channel processes a signal that is used to establish the background reference level. The second channel is used to observe the engine during the time interval that preignition may be expected. This information is compared with the "background" signal via the IC's integrator and will tend to cancel the background noise and accentuate noise due to engine pre-detonation. Moreover, the bandpass of filter channels can be optimized to further discriminate between engine background and combustion noise and pre-detonation noise. A basic approach to engine pre-detonation systems is to only observe engine background during the time interval that noise is expected and if detected, retard timing. This approach does not require the sensitivity and selectivity that is needed for a continuously adjustable solution. Enhanced fuel economy and performance is obtainable when this IC is coupled with a microprocessor controlled fuel management system. In a typical application the input signal frequency may vary from DC to 20kHz. External capacitors are used to decouple the IC from the sensor (C1 and C2). A typical value of the capacitors is 3.3nF. Series input resistors, R1 and R2, are used to connect the inverting inputs of the amplifiers, (pins 20 and 17). Feedback resistors, R3 and R4, in conjunction with R1 and R2 are used to set the gain of the amplifiers.
SENSOR C1 0 VMID R1 PIN 20 PIN 3 R4 C2 1 VMID R2 PIN 17 PIN 3 R3
+ PIN 19
SENSOR
+ PIN 18
FIGURE 3. INPUT AMPLIFIER CONNECTIONS
A mid-voltage level is generated by the IC. This level is set to be half way between VDD and ground. Throughout the IC this level is used as a quiet, DC reference for the circuits within the IC. This point is brought out for several reasons: it can be used as a reference voltage, and it must be bypassed to ensure that it is a quiet reference for the internal circuitry. The input amplifiers are designed with power down capability, which, when activated disables their bias circuit and their output goes into a three-state condition. This is very important during the test mode, in which the output terminals of the amplifiers are driven by the outside world with test signals.
Antialiasing Filter
The IC has a 3rd order Butterworth filter with a -3dB point at 70kHz. Double poly-silicon capacitors and implanted resistors are used to set poles in the filter. This filter is required to have no more than 1dB attenuation at 20kHz (highest frequency off interest) and a minimum attenuation of 10dB at 180kHz. This filter precedes the switch capacitor filters which run at 200kHz.
Circuit Block Description
Input Amplifiers
Two amplifiers are used to interface to the two engine sensors. These amplifiers have a typical open loop gain of 100dB, with a typical bandwidth of 2.6MHz. The common mode input voltage range extends to within 0.5V of either supply rail. The amplifier output has a similar output range. Sufficient gain, bandwidth and output swing capability was provided to ensure that the amplifiers can handle attenuation gain settings of 20 to 1 or -26dB. This would be needed when high peak output signals, in the range of 8VRMS , are obtained from the transducer. Gain settings of 10 times can also be needed when the transducers have output levels of 5mVRMS .
Programmable Band Pass Switched Capacitor Filters
Two identical programmable filters are used to detect the two frequencies of interest. The Knock Frequency Filter is programmed to pass the frequency component of the engine knock. The Reference Frequency Filter is used to detect background noise at a second programmed frequency. The filter frequency is established by the characteristics of the particular engine and transducer. By subtracting the energy component of these two filters, we can detect if a knock has occurred. The filters have a nominal differential gain of 4. Their frequency is set by program words (discussed in the Communications Protocol section). Center frequencies can be programmed from 1.22kHz to 19.98kHz, in 64 steps. The filter Qs are typically 2.4.
4-6
HIP9010
Balance/Gain Adjust Stage
The gains from the Knock Frequency Filter and the Reference Frequency Filter can be adjusted with respect to one another, so that the difference energies in the two bands can be compensated. This balance is achieved by feeding one of the filters unattenuated (gain = 1) and attenuating the other. This can be adjusted with 64 different gain settings, ranging between 1 and 0.133. The signals can swing between 20 and 80 percent of VDD. Programming is discussed in the Communications Protocol section. The test/channel attenuate word is used to determine which of the two channels is attenuated and which is set to unity gain.
Differential to Single-Ended Converter
This signal takes the output of the two integrators (through the test-multiplexer circuit) and provides a signal that is the sum of the two signals. This technique is used to improve the noise immunity of the system.
Output Buffer
This output amplifier is the same amplifier circuits as the input amplifier used to interface with the sensors. When the output of the antialiasing filter is tested, this amplifier is in the power down mode.
Communications Protocol
The multiprocessor talks to the knock sensor via an SPI bus (MOSI). A chip select pin (CS) is used to enable the chip, which, in conjunction with the SPI clock (SCK), moves in the eight bit programming word. Five different programming words are used to set gains, frequency response, integrator constants, test mode, channel select and test mode conditions. With chip select (CS) going low, on the next rising edge of the SPI clock (SCK), data is latched into the IC. The data is shifted with the most significant bit first and least significant bit last. Each word is divided into two parts: first the address and then the value. Depending on the function being controlled, the address is 2 or 3 bits, and the value is either 5 or 6 bits long. During the hold mode of operation, all five programming words can be entered into the IC, but during the integrate time any single byte may be entered but will not be acted upon until the start of the next hold period. The integration or hold mode of operation is controlled by the INT/HOLD input signal.
Active Full Wave Rectifier
The output of the filters are independently full wave rectified using switch capacitor techniques. Each of two rectifier circuits provide both negative and positive values for the knock frequency and reference frequency filter outputs. The output is able to swing from 20% to 80% of VDD. Care was taken to minimize the RMS variations from input to output of this section.
Integrator Stage
The signals from the two rectifiers are summed and integrated together. A differential system is used to reduce noise. One system integrates the positive energy of the Knock Frequency Rectifier with respect to the positive energy of the Reference Frequency Rectifier. The second system does the integration of the negative energy value of the two rectifiers. The positive and negative energy signals are opposite phase signals. Using this technique reduces system noise. The integrator time constant is software programmable by the Integrator Time Constant discussed in the Communications Protocol section. The time constant can be programmed from 40s to 600s, with a total of 32 steps. If for example, we program a time constant to 200s, then with one volt difference between each channel, the output of the integrator will change by 1 volt in 200s. When integration is enabled by the rising edge of the INT/HOLD input, the output of the integrator will fall to 0.5V, within 20s after the integrate line reaches the integrate state. The output of the integrator is an analog voltage.
Programming Words
1. Reference Filter Frequency: Defines the center frequency of the Reference Filter in the system. The first 2 bits are used for the address and the last 6 bits are used for its value. 01FFFFFF Example: 01001010 would be the reference filter (01 for the first two bits) at a center frequency of 1.78kHz (bit value in Table 2 of 10). 2. Knock Filter Frequency: Defines the center frequency of the Knock Filter in the system. The first 2 bits are used for the address and the last 6 bits are used for its value. 00FFFFFF Example: 00100111 would be the knock filter frequency (00 for the first two bits) at a center frequency of 6.37kHz (bit value in Table 2 of 39). 3. Balance Control: Defines the ratio of the gain of the knock band center frequency to that of the reference band center frequency. This role can be reversed by the value of CA in the fifth programming bit, as explained in 5, Test/Channel Select/Channel Attenuate Control. The first 2 bits are used for the address and the last 6 bits for its value. 10GGGGGG Example: 10010100 would be the balance control (10 for the first two bits) with an attenuation of 0.514 (bit value in Table 2 of 20.) Depending on the value of CA in the fifth word this would apply to the reference or the knock gain section.
Test Multiplexer
This circuit receives the positive and negative outputs from the two integrators, together with the outputs from different parts of the IC. The output is controlled by the fifth programming word of the communications protocol. This multiplexes the switch capacitor filter output, the gain control output and the antialiasing filter output.
4-7
HIP9010
4. Integrator Time Constant: Defines the Integration Time Constant for the system. The first 3 bits are used for the address and the last 5 bits for the value. 110TTTTT Example: 11000011 would be the integrator time constant (110 on for the first 3 bits) and an integration constant of 55s (bit value of 3 in Table 2). 5. Test/Channel Select/Channel Attenuate Control: This word serves several purposes. By looking at the structure, 111TATBTCCSCA , the first 3 bits are used for the address, and the last 5 bits are used for the value. The options are: - If CS is "0" channel "0" is selected. If CS is "1" channel "1" is selected. - If CA is "0" attenuation applies to the knock filter. If CA is "1" attenuation applies to the reference filter. - During the test mode (TEST input is a low level), if TA is "0" all sections get their input from the output of the antialiasing filter input. This input can come from either the output of channel "0" amplifier or channel "1" output depending upon the state of the CS bit. If TA is "0" the input amplifiers are powered down. If TA is set to "1" during the test mode the chip is configured in its normal operating state, getting inputs to all sections from previous sections. - Combinations of TA , TB and TC are used to test the different analog parts of the circuit. Table 1 shows these combinations. All blocks except for the antialiasing filter are sampled via the differential to single ended converter in the test mode.
TABLE 1. SHOWING PROGRAMMING IN THE TEST MODE TEST PIN 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 NOTE: 3. All Test function blocks have their outputs buffered by the differential to single ended converter. Their outputs are available at the INTOUT pin 4 of the chip. In the case of the antialias filter test function, the output is taken directly to the INTOUT pin 4 of the chip. FIGURE 4D. S0FB, S1FB AND INOUT EQUIVALENT OUTPUT CIRCUITS FIGURE 4. INTERFACE CIRCUITS TA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x TB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x TC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x CHS 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x ANALOG OUTPUT FROM: Knock Rectifier Reference Knock Filter Reference Filter Antialias Filter(1) Antialias Filter(1) Integrator Integrator Knock Rectifier Reference Knock Filter Reference Filter Antialias Filter(1) Antialias Filter(1) Integrator Integrator Integrator
S0FB S1FB INOUT VDD 50A TO LOGIC TEST 14 V DD
S0IN S1IN
TO NEXT STAGE
HALF OF DIFFERENTIAL AMPLIFIER
FIGURE 4A. S0IN AND S1IN INPUT CIRCUIT
MISO 11
FIGURE 4B. MISO OUTPUT OF SPI DATA BUS IS AN OPEN DRAIN TRANSISTOR
VDD
FIGURE 4C. TEST PMOS TRANSISTOR HAS EQUIVALENT CURRENT PULLUP CAPABILITY OF A 50k TO 200k RESISTOR
4-8
HIP9010
TABLE 2. FREQUENCY, BALANCE / GAIN AND INTEGRATOR TIME CONSTANT SETTINGS BIT VALUE PER FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 FREQUENCY kHz 1.22 1.26 1.31 1.35 1.40 1.45 1.51 1.57 1.63 1.71 1.78 1.87 1.96 2.07 2.18 2.31 2.46 2.54 2.62 2.71 2.81 2.92 3.03 3.15 3.28 3.43 3.59 3.76 3.95 4.16 4.39 4.66 OUTPUT LEVEL 1.000 0.960 0.923 0.889 0.857 0.828 0.800 0.774 0.750 0.727 0.706 0.686 0.667 0.649 0.632 0.615 0.600 0.576 0.554 0.533 0.514 0.497 0.480 0.465 0.450 0.436 0.424 0.411 0.400 0.389 0.379 0.369 TIME CONSTANT s 40 45 50 55 60 65 70 75 80 90 100 110 120 130 140 150 160 180 200 220 240 260 280 300 320 360 400 440 480 520 560 600 BIT VALUE PER FUNCTION 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 FREQUENCY kHz 4.95 5.12 5.29 5.48 5.68 5.90 6.12 6.37 6.64 6.94 7.27 7.63 8.02 8.46 8.95 9.50 10.12 10.46 10.83 11.22 11.65 12.10 12.60 13.14 13.72 14.36 15.07 15.84 16.71 17.67 18.76 19.98 OUTPUT LEVEL 0.360 0.346 0.333 0.320 0.309 0.298 0.288 0.279 0.270 0.262 0.254 0.247 0.240 0.234 0.228 0.222 0.217 0.208 0.200 0.193 0.186 0.179 0.173 0.168 0.163 0.158 0.153 0.149 0.144 0.141 0.137 0.133
4-9
HIP9010
ADDRESS DECODER
MOSI
REFERENCE FILTER DIGITAL MULTIPLEXER KNOCK FILTER SPI INTERFACE
SCK
BALANCE CONTROL INTEGRATOR TIME CONSTANT TEST/ CHANNEL SELECT ATTENUATE OSCILLATOR CIRCUIT MOSI TEST COMPARATOR OUT (FROM RECTIFIER PHASE DETECTOR)
CS
MISO
OSCIN
OSCOUT
FIGURE 5. DIGITAL BLOCK DIAGRAM
The digital block diagram shows the programming flow of the chip. An eight bit word is received at the MISO port. Data is shifted in by the SCK clock when the chip is enabled by the CS pin. The word is decoded by the address decoding circuit, and the information is directed to one of 5 registers. These registers control: 1. Reference knock filter frequency. 2. Knock filter frequency. 3. Balance control or attenuation of one channel with respect to the other. 4. Integration time constant of the sum of the two channels. 5. One of 3 functions. a) test conditions of the part. b) channel select to one of two sensors. c) channel to be attenuated. A crystal oscillator circuit is provided. The chip requires a 4MHz crystal to be connected across OSCIN and OSCOUT pins. In the test mode, use the digital multiplexer to output one of the following signals: 1. Contents of one of the five registers in the chip. 2. Inverted signal of the MOSI pin. 3. Voltage of an internal comparator used to rectify the analog signal.
INT/HOLD T8 CS T1 SCK T2 DATA IN T6 T7 B7 T3 B6 B5 B4 B3 B2 B1 B0 T4 T5
FIGURE 6. SPI TIMING
TABLE 3. SPI TIMING REQUIREMENTS DESCRIPTION T1 minimum time from CS falling edge to SCK falling edge. T2 minimum time from CS falling edge to SCK rising edge. T3 minimum time for the SCK low. T4 minimum time for the SCK high. T5 minimum time from SCK rise after 8 bits to CS rising edge. T6 minimum time from data valid to rising edge of SCK. T7 minimum time for data valid after the rising edge of the SCK. T8 minimum time after CS rises until INT/HOLD goes high. UNITS 10ns 80ns 60ns 60ns 80ns 60ns 10ns 8s
Upon power up, chip requires that the INT/HOLD pin is toggled. If this is not done then it is important to note, that only the first result and SPI data bytes sent after power up will not be valid. Any subsequent chip operation will then be performed correctly.
4-10
HIP9010
Test Multiplexer
CS
INT/HOLD
FIGURE 7. POWER UP SEQUENCE
This circuit receives the positive and negative outputs out of the two integrators, together with the outputs from different parts of the chip. The output is controlled by the fifth programming word of the communications protocol. This multiplexes the switch capacitor filter output, the gain control output as well as the antialias output.
Differential to Single-ended Converter
This signal takes the output of the two integrators (through the test multiplexer circuit) and provides a signal that is the sum of the two signals. This technique is used to improve the noise immunity of the system.
T1 INT/HOLD T2
T3
Output Buffer
T4
INTOUT
This output amplifier is the same as the input amplifier used to interface to the sensors. For test purposes when we look at the output of the antialias filter, the input amplifiers are in the power down mode.
FIGURE 8. INTEGRATOR TIMING TABLE 4. INTERGRATE/HOLD TIMING REQUIREMENTS DESCRIPTION T1 maximum rise time of the INT/HOLD signal. T2 maximum time after INT/HOLD rises for the INOUT to begin to intergrate. T3 maximum fall time of INT/HOLD signal. T4 typical time after INT/HOLD goes low before chip goes into hold state. T5 minimum INT/HOLD time during power up sequence. UNITS 45ns 20s 45ns 20s 1s
4-11
HIP9010 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 12.60 7.40 MAX 2.65 0.30 0.51 0.32 13.00 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.4961 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.5118 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.394 0.010 0.016 20 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 20 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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